B-6 Sun Fire X4100/X4100 M2 and X4200/X4200 M2 Servers Service Manual • August 2009
B.5 POST Code Checkpoints
The POST code checkpoints are the largest set of checkpoints during the BIOS pre-
boot process.
TABLE B-2 describes the type of checkpoints that might occur during the
POST portion of the BIOS. These two-digit checkpoints are the output from primary
I/O port 80.
TABLE B-2 POST Code Checkpoints
Post Code Description
03 Disables the NMI, parity, video for the EGA, and the DMA controllers. At this point, only
ROM accesses are to the GPNV. If the BB size is 64K, requires turning on ROM decode
below FFFF0000h. It should allow the USB to run in the E000 segment. Though the HT
must program the NB-specific initialization, it can also program the OEM-specific
initialization if needed at the beginning of BIOS POST, for instance to override default
kernel variables.
04 Checks the CMOS diagnostic byte to determine if battery power is OK and the CMOS
checksum is OK. Verifies the CMOS checksum manually by reading storage area. If the
CMOS checksum is bad, updates the CMOS with power-on default values and clears
passwords. Initializes status register A. Initializes data variables based on the CMOS setup
questions. Initializes both 8259-compatible PICs in the system.
05 Initializes the interrupt controlling hardware (generally PIC) and the interrupt vector
table.
06 Performs R/W test to the CH-2 count reg. Initializes CH-0 as the system timer. Installs the
POSTINT1Ch handler. Enables IRQ-0 in the PIC for system timer interrupt. Traps the
INT1Ch vector to POSTINT1ChHandlerBlock.
C0 Starts early CPU initialization, disables Cache, initializes local APIC.
C1 Sets up the boot strap processor information.
C2 Sets up the boot strap processor for POST. This includes frequency calculation, loading
BSP microcode, and applying user requested value for the GART Error Reporting setup
question.
C3 Applies errata workarounds to the BSP (#78 & #110).
C5 Enumerates and sets up application processors. This includes microcode loading and
workarounds for errata (#78, #110, #106, #107, #69, #63).
C6 Re-enables cache for boot strap processor, and applies workarounds in the BSP for errata
#106, #107, #69, and #63 if appropriate. In case of mixed CPU steppings, errors are sought
and logged, and an appropriate frequency for all CPUs is found and applied. APs are left
in the CLI HLT state.
C7 The HT sets link frequencies and widths to their final values. This routine is called after
CPU frequency has been calculated to prevent bad programming.
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