Appendix B BIOS POST Codes B-7
0A Initializes the 8042-compatible Keyboard Controller.
0B Detects the presence of a PS/2 mouse.
0C Detects the presence of a keyboard in the KBC port.
0E Tests and initializes different input devices. Also updates kernel variables. Traps the
INT09h vector so that the POST INT09h handler gets control for IRQ1. Decompresses all
available language, BIOS logo, and silent logo modules.
13 Initializes PM regs and PM PCI regs at early POST. Initializes multi host bridge if the
system supports it. Sets up ECC options before memory clearing. REDIRECTION causes
corrected data to be written to RAM immediately. CHIPKILL provides 4 bit error det/corr
of x4 type memory. Enables PCI-X clock lines in the 8131.
20 Relocates all CPUs to a unique SMBASE address. Sets the BSP to have its entry point at
A000:0. If less than 5 CPU sockets are present on a board, subsequent CPU entry points are
separated by 8000h bytes. If more than four CPU sockets are present, entry points are
separated by 200h bytes. The CPU module relocates the CPU to the correct address. APs
are left in the INIT state.
24 Decompresses and initializes any platform-specific BIOS modules.
30 Initializes System Management Interrupt.
2A Initializes different devices through DIM.
2C Initializes different devices. Detects and initializes the video adapter installed in systems
that have optional ROMs.
2E Initializes all the output devices.
31 Allocates memory for the ADM module and decompresses it. Gives control to the ADM
module for initialization. Initializes language and font modules for the ADM. Activates
the ADM module.
33 Initializes the silent boot module. Sets the window for displaying text information.
37 Displays sign-on message, CPU information, setup key message, and any OEM-specific
information.
38 Initializes different devices through the DIM.
39 Initializes DMAC-1 and DMAC-2.
3A Initializes RTC date/time.
3B Tests for total memory installed in the system. Also checks for DEL or ESC keys to limit
memory test. Displays total memory in the system.
3C Signals that the RAM read/write test is completed, and programs memory holes or
handles any adjustments needed in RAM size for the NB. Tests if the HT module found an
error in the boot block and for CPU compatibility with the MP environment.
40 Detects different devices (parallel ports, serial ports, and the coprocessor in the CPU, etc.)
that are successfully installed in the system and updates the BDA, EBDA and so on.
TABLE B-2 POST Code Checkpoints (Continued)
Post Code Description
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