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List of Tables
0-1. CC253x Family Overview ................................................................................................ 16
0-2. Register Bit Conventions ................................................................................................. 17
2-1. SFR Overview.............................................................................................................. 31
2-2. Overview of XREG Registers ............................................................................................ 35
2-3. Instruction Set Summary ................................................................................................. 40
2-4. Instructions That Affect Flag Settings .................................................................................. 43
2-5. Interrupts Overview........................................................................................................ 44
2-6. Priority Level Setting ...................................................................................................... 50
2-7. Interrupt Priority Groups .................................................................................................. 50
2-8. Interrupt Polling Sequence ............................................................................................... 51
3-1. Debug Commands ........................................................................................................ 56
3-2. Debug Configuration ...................................................................................................... 58
3-3. Debug Status............................................................................................................... 58
3-4. Relation Between PCON_IDLE and PM_ACTIVE ......................................................................... 59
3-5. Flash Lock-Protection Bit Structure Definition ......................................................................... 60
4-1. Power Modes .............................................................................................................. 64
6-1. Example Write Sequence ................................................................................................ 77
7-1. Peripheral I/O Pin Mapping .............................................................................................. 83
8-1. DMA Trigger Sources ................................................................................................... 101
8-2. DMA Configuration Data Structure .................................................................................... 102
9-1. Initial Compare Output Values (Compare Mode) .................................................................... 111
9-2. Frequency Error Calculation for 38-kHz Carrier ..................................................................... 115
10-1. Initial Compare Output Values (Compare Mode) .................................................................... 127
13-1. Values Showing How Different Temperatures Relate to BATTMON_VOLTAGE for a Typical Device ....... 146
13-2. Values for A and B (for a Typical Device) When Using the Battery monitor for Temperature Monitoring ... 147
17-1. Commonly Used Baud-Rate Settings for 32 MHz System Clock.................................................. 166
20-1. Slave Transmitter Mode................................................................................................. 181
20-2. Slave Receiver Mode.................................................................................................... 182
20-3. Master Transmitter Mode ............................................................................................... 184
20-4. Master Receiver Mode .................................................................................................. 185
20-5. Miscellaneous States.................................................................................................... 187
20-6. Clock Rates Defined at 32 MHz........................................................................................ 188
21-1. USB Interrupt Flags Interrupt-Enable Mask Registers .............................................................. 193
21-2. FIFO Sizes for EP 1–5 .................................................................................................. 196
22-1. Internal Registers ........................................................................................................ 213
23-1. Frame Filtering and Source Matching Memory Map ................................................................ 225
23-2. IEEE 802.15.4-2006 Symbol-to-Chip Mapping....................................................................... 227
23-3. FSM State Mapping ..................................................................................................... 247
23-4. Instruction Set Summary................................................................................................ 253
23-5. Register Overview ....................................................................................................... 266
23-6. Registers That Require Update From Their Default Value ......................................................... 267
23-7. Register-Bit Access Modes............................................................................................. 267
25-1. Radio RAM Pages ....................................................................................................... 293
25-2. Commands to FIFO via RFST Register............................................................................... 296
25-3. Access to FIFO Registers............................................................................................... 297
25-4. RAM-Based Registers................................................................................................... 298
25-5. Address Structure for Auto Mode...................................................................................... 302
13
SWRU191C–April 2009–Revised January 2012 List of Tables
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