Xantrex XTR 6-110 - Figure 5-17 IEEE 488.2 Register Model; Status Registers Model from IEEE 488.2

Status Registers Model from IEEE 488.2
M370046-01 5-27
5
Status Registers Model from IEEE 488.2
The IEEE 488.2 registers shown in the bottom rectangle of Figure 5-16
follow the IEEE 488.2 model for status registers. The IEEE 488.2 register
only has enable registers for masking the summary bits. Figure 5-17
shows the details on the relationship between the mask/enable registers
and the summary bits. Sections describing the bits for both registers will
follow Figure 5-17.
Figure 5-17 IEEE 488.2 Register Model
SERS Enable
Register
0
1
2
3
4
5
6
7
Standard
Event Status
Register
(SESR )
+
SESR
Summary
Bit
...
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
&
&
&
&
&
&
&
&
Status Byte
Enable Register
0
1
2
3
4
5
6
7
Status Byte
Register
&
&
&
&
&
&
&
+
MSS
Summary
Bit
QUEStionable SCPI Register
Summary Bit
OPERational SCPI Register
Summary Bit
Error/Event Queue Status Flag
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