Xilinx KCU116 - Page 22

KCU116 Board User Guide 22
UG1239 (v1.2) September 28, 2018 www.xilinx.com
Chapter3: Board Component Descriptions
The KCU116 dual DDR4 memory component interface adheres to the constraints guidelines
documented in the “DDR3/DDR4 Design Guidelines” section of the UltraScale
Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) [Ref 5]. The
KCU116 board DDR4 memory component interface is a 40 impedance implementation.
For more details about the Micron DDR4 component memory, see the Micron
MT40A256M16GE-075E data sheet at the Micron website [Ref 23].
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