Xilinx KCU116 - Appendix B: Xilinx Constraints File; Overview

KCU116 Board User Guide 82
UG1239 (v1.2) September 28, 2018 www.xilinx.com
Appendix B
Xilinx Constraints File
Overview
The Xilinx
®
design constraints (XDC) file template for the KCU116 board is for designs
targeting the KCU116 evaluation board. Net names in the constraints correlate with net
names on the latest KCU116 evaluation board schematic. Users must identify the
appropriate pins and replace the net names with net names in the user RTL. See the Vivado
Design Suite User Guide: Using Constraints (UG903) [Ref 13] for more information.
The FMC connector J5 (HPC0) is connected to a 1.8V V
ADJ
bank. Because different FMC
cards implement different circuitry, the FMC bank I/O standards must be uniquely defined
by each customer.
IMPORTANT: The XDC file can be accessed on the Kintex UltraScale+ FPGA KCU116 Evaluation Kit
website.
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