Xilinx KCU116 - Clock Generation

KCU116 Board User Guide 28
UG1239 (v1.2) September 28, 2018 www.xilinx.com
Chapter3: Board Component Descriptions
Clock Generation
[Figure 2-1, callout 6]
The KCU116 evaluation board provides eight clock sources to the XCKU5P device as listed in
Table 3-5.
Table3‐5: KCU116 Board Clock Sources
Clock Name Clock Ref. Des. Description
System clock 300 MHz U170
Silicon Labs Si5335A 1.8V LVDS any frequency quad
clock generator CLK0. See System Clock (SYSCLK_300_P
and SYSCLK_300_N).
System clock 125 MHz U170
Silicon Labs Si5335A 1.8V LVDS any frequency quad
clock generator CLK1. See System Clock (CLK_125MHZ).
EMC clock 90 MHz U170
Silicon Labs Si5335A 1.8V LVCMOS single-ended any
frequency quad clock generator CLK2. See System Clock
(FPGA_EMCCLK).
System control clock 33.333 MHz U170
Silicon Labs Si5335A 1.8V LVCMOS single-ended any
frequency quad clock generator CLK3. See System Clock
(SYSCTLR_CLK).
User MGT clock 10 MHz–810 MHz U56
Silicon Labs Si570 3.3V LVDS I
2
C programmable
oscillator, 156.250 MHz default.
(USER_MGT_SI570_CLOCK_P and
USER_MGT_SI570_CLOCK_N).
User SMA clock J168(P), J169(N)
User clock input SMAs. See User SMA Clock
(USER_SMA_CLOCK_P and USER_SMA_CLOCK_N).
Jitter attenuated clock U20
Silicon Labs Si5328C LVDS precision clock
multiplier/jitter attenuator. See Jitter Attenuated Clock
(SFP_SI5328_OUT_P and SFP_SI5328_OUT_N).
Video clock 74.25 MHz U179
Silicon Labs Si511 3.3V LVDS fixed frequency oscillator.
See Video Clock (CLK_74_25_P and CLK_74_25_N).
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