Description of CEI-100/200 ARINC Interface Enabling Interrupts
CEI-100/CEI-200/CEI-x20 User’s Manual 163
On the CEI-100 this is programmed using the slave status word at location:
0464h
where if bit 2 is set, time tagging is enabled, otherwise it is disabled.
This word contains other data that must be maintained when updating
these bits.
Enabling Interrupts
The slave interrupts the host upon receipt of data on any particular channel
(seeAR_INT_CONTROL). To enable this function on the CEI-200, write
to the interrupt control status word at location:
04D8h
where the LS bit represents channel 1 and bit 7 represents channel 8.
A 0 bit disables the interrupt function and a 1 enables the interrupt
function for that channel.
On the CEI-100 the slave status word at location:
0464h
controls this with bit 0 for receiver 1 and bit 1 for receiver 2. The
CEI-100 slave status word contains other information that must be
preserved when modifying these bits.
This function can be used while the board is running.
Receiving Data
As data is received, it is stored in locations in dual-port RAM by the on-
board processor. See AR_SET_STORAGE_MODE for a complete
description of these modes. There are three storage modes: BUFFERED,
DEDICATED, and MERGED.
In BUFFERED mode, each channel has its own circular buffer. As data
comes in, the ARINC board continuously places it at the end of the buffer.
It is your responsibility to retrieve data from the buffer fast enough so it is
not overwritten. Each buffer has a four-word data structure that controls
access to it:
word 0: buffer segment
word 1: wrap mask
word 2: head pointer
word 3: tail pointer
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