abaco systems CEI-520 - Appendix A Modifying CEI-200 Base Bit Rate; Procedure; Table 48. Calculating a Clock-Scaling Factor

CEI-100/CEI-200/CEI-x20 User’s Manual 167
APPENDIX A
Modifying CEI-200 Base Bit Rate
Procedure
The CEI-200 provides multiple ARINC 429 channels. Standard high
(100Kbs) and low (12.5Kbs) bit rates are supported by default. To use the
hardware at different bit rates, the following procedures may be used. You
must know what base address the board has been configured to use.
First, you must calculate a clock-scaling factor from the following table,
based upon the desired bit rate:
Table 48. Calculating a Clock-Scaling Factor
Scaling
A
B
Bit Rate (“HI”)
Max
Min
1:1
2
2
100K
125K
83K
1:2
4
4
50K
62.5K
41.5K
1:5
10
10
20K
25K
16.6K
1:9.5
19
19
10.5K
13.1K
8.7K
1:10
20
20
10K
12.5K
8.3K
1:10.5
21
21
9.5K
11.9K
7.9K
1:11
22
22
9.1K
11.3K
7.4K
Virtually any other scaling factor is achievable, based on the following
formula:
(A+B)*2.5 = number of microseconds per bit.
In Table 48, a scaling of 1:1 is the default. The A and B values are used
for scaling the clock on the CEI-200 as described in the following
procedures. The Bit Rate “HI” setting is the actual bit rate (in bits/second)
that corresponds to the “High” setting (as programmed using the utility
libraries or menu selections.)
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