Abov MC96F6432S Series User Manual

213
MC96F6432S
ABOV Semiconductor Co., Ltd.
USInCR2 (USIn Control Register 2: For UART, SPI, and I2C mode): DAH/EAH, n = 0, 1
7
6
5
4
3
2
1
0
DRIEn
TXCIEn
RXCIEn
WAKEIEn
TXEn
RXEn
USInEN
DBLSn
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
DRIEn
Interrupt enable bit for data register empty (only UART and SPI mode).
0
Interrupt from DREn is inhibited (use polling)
1
When DREn is set, request an interrupt
TXCIEn
Interrupt enable bit for transmit complete (only UART and SPI mode).
0
Interrupt from TXCn is inhibited (use polling)
1
When TXCn is set, request an interrupt
RXCIEn
Interrupt enable bit for receive complete (only UART and SPI mode).
0
Interrupt from RXCn is inhibited (use polling)
1
When RXCn is set, request an interrupt
WAKEIEn
Interrupt enable bit for asynchronous wake in STOP mode. When device is in stop
mode, if RXDn goes to low level an interrupt can be requested to wake-up system.
(only UART mode). At that time the DRIEn bit and USInST1 register value should be
set to ‘0b’ and “00H”, respectively.
0
Interrupt from Wake is inhibited
1
When WAKEn is set, request an interrupt
TXEn
Enables the transmitter unit (only UART and SPI mode).
0
Transmitter is disabled
1
Transmitter is enabled
RXEn
Enables the receiver unit (only UART and SPI mode).
0
Receiver is disabled
1
Receiver is enabled
USInEN
Activate USIn function block by supplying.
0
USIn is disabled
1
USIn is enabled
DBLSn
This bit selects receiver sampling rate (only UART).
0
Normal asynchronous operation
1
Double Speed asynchronous operation

Abov MC96F6432S Series Specifications

General

Brand	Abov
Model	MC96F6432S Series
Category	Microcontrollers
Language	English