Abov MC96F6432S Series - Page 215

215
MC96F6432S
ABOV Semiconductor Co., Ltd.
USI0CR4 (USIn Control Register 4: For I2C mode): DCH/ECH, n = 0, 1
7
6
5
4
3
2
1
0
IICnIFR
–
TXDLYENBn
IICnIE
ACKnEN
IMASTERn
STOPCn
STARTCn
R
–
R/W
R/W
R/W
R
R/W
R/W
Initial value: 00H
IICnIFR
This is an interrupt flag bit for I2C mode. When an interrupt occurs, this bit becomes ‘1’.
This bit is cleared when all interrupt source bits in the USInST2 register are cleared to
“0b”. Writing “1” has no effect.
0
I2C interrupt no generation
1
I2C interrupt generation
TXDLYENBn
USInSDHR register control bit
0
Enable USInSDHR register
1
Disable USInSDHR register
IICnIE
Interrupt Enable bit for I2C mode
0
Interrupt from I2C is inhibited (use polling)
1
Enable interrupt for I2C
ACKnEN
Controls ACK signal Generation at ninth SCLn period.
0
No ACK signal is generated (SDAn =1)
1
ACK signal is generated (SDAn =0)
NOTE) ACK signal is output (SDA =0) for the following 3 cases.
1. When received address packet equals to USInSLA bits in USInSAR.
2. When received address packet equals to value 0x00 with GCALLn
enabled.
3. When I2C operates as a receiver (master or slave)
IMASTERn
Represent operating mode of I2C
0
I2C is in slave mode
1
I2C is in master mode
STOPCn
When I2C is master, STOP condition generation
0
No effect
1
STOP condition is to be generated
STARTCn
When I2C is master, START condition generation
0
No effect
1
START or repeated START condition is to be generated