Abov MC96F6432S Series - Page 230

230
MC96F6432S
ABOV Semiconductor Co., Ltd.
LCDCCR (LCD Driver Contrast Control Low Register): 9BH
7
6
5
4
3
2
1
0
LCTEN
–
–
–
VLCD3
VLCD
VLCD1
VLCD0
R/W
–
–
–
R/W
R/W
R/W
R/W
Initial value: 00H
LCTEN
Control LCD Driver Contrast
0
LCD Driver Contrast disable
1
LCD Driver Contrast enable
VLCD[3:0]
VLC0 Voltage Control when the contrast is enabled
VLCD3
VLCD 2
VLCD 1
VLCD 0
Description
0
0
0
0
VLC0 = VDD x 16/31 step
0
0
0
1
VLC0 = VDD x 16/30 step
0
0
1
0
VLC0 = VDD x 16/29 step
0
0
1
1
VLC0 = VDD x 16/28 step
0
1
0
0
VLC0 = VDD x 16/27 step
0
1
0
1
VLC0 = VDD x 16/26 step
0
1
1
0
VLC0 = VDD x 16/25 step
0
1
1
1
VLC0 = VDD x 16/24 step
1
0
0
0
VLC0 = VDD x 16/23 step
1
0
0
1
VLC0 = VDD x 16/22 step
1
0
1
0
VLC0 = VDD x 16/21 step
1
0
1
1
VLC0 = VDD x 16/20 step
1
1
0
0
VLC0 = VDD x 16/19 step
1
1
0
1
VLC0 = VDD x 16/18 step
1
1
1
0
VLC0 = VDD x 16/17 step
1
1
1
1
VLC0 = VDD x 16/16 step
NOTE) The LCD contrast step is based on 1/4 bias and RLCD=60kΩ.
1. 1/4 bias : VDD x 16/(31 – VLC[3:0]) when RLCD= 60kΩ
VDD x 32/(47 – VLC[3:0]) when RLCD= 120kΩ
2. 1/3 bias : VDD x 12/(27 – VLC[3:0]) when RLCD= 60kΩ
VDD x 24/(39 – VLC[3:0]) when RLCD= 120kΩ
3. 1/2 bias : VDD x 8/(23 – VLC[3:0]) when RLCD= 60kΩ
VDD x 16/(31 – VLC[3:0]) when RLCD= 120kΩ