Abov MC96F6432S Series - Page 238

238
MC96F6432S
ABOV Semiconductor Co., Ltd.
Figure 13.5 Configuration Timing when Power-on
Figure 13.6 Boot Process WaveForm
Reset Release
Configure Read
POR
:VDD Input
:Internal OSC
①
②
③
④
⑤
⑥
⑦
VDD
Internal nPOR
PAD RESETB
BIT (for Configure)
LVR_RESETB
BIT (for Reset)
INT-OSC 8 MHz/8
INT-OSC (8 MHz)
RESET_SYSB
Configure Read
1us X 256 X 28h = about 10ms
1us X 4096 X 4h = about 16ms
00
01
02
03
00
..
27
28
F1
Counting for configure read start after POR is released
“H”
INT-OSC 8MHz / 8 = 1MHz (1us)
00
01
01
02
03
04
05
00