Abov MC96F6432S Series - Page 239

239
MC96F6432S
ABOV Semiconductor Co., Ltd.
Process
Description
Remarks
①
- No Operation
②
-1st POR level Detection
-about 1.4V
③
- (INT-OSC 8MHz/8)x256x28h Delay section (=10ms)
-VDD input voltage must rise over than flash operating
voltage for Configure option read
-Slew Rate >= 0.05V/ms
④
- Configure option read point
-about 1.5V ~ 1.6V
-Configure Value is determined by Writing
Option
⑤
- Rising section to Reset Release Level
-16ms point after POR or Ext_reset release
⑥
- Reset Release section (BIT overflow)
i) after16ms, after External Reset Release (External reset)
ii) 16ms point after POR (POR only)
- BIT is used for Peripheral stability
⑦
-Normal operation
Table 13.2 Boot Process Description