Internal Test Descriptions
This chapter describes the power-on test, calibration routine, fault log
messages, and self tests. This chapter also contains a list of the GPIB
commands for each self test.
Power-on Test Description
The power-on test is run when the analyzer is powered up. The calibration routine is
run immediately following the power-on test. The power-on test exercises the
A7 CPU assembly and A8 Memory assembly. This test is divided into low-level and
high-level subtests.
Low-level Subtests
The low-level power-on subtests exercise the core of the A7 CPU assembly and A8
Memory assembly. If an error occurs during the low-level subtests, the test stops and
displays an error code on the A7 CPU assembly’s power-on test LEDs.
High-level Subtests
The high-level power-on subtests exercise the fast bus and the multi-function
peripheral on the A7 CPU assembly. The high-level subtests are also self tests (see
‘’Self-Test Descriptions’’). If an error occurs during the high-level subtests, an error
message is entered in the test log.
10-2
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