Using Wideband CDMA ESG-D Series Option H98 Signal Generators
Understanding Time Offsets
3-10 Manual Supplement
Figure 3-2 Time Offsets in Uplink Mode
BTS Reference
SFN Reset Input
(PATTERN TRIG IN
Rear-Panel BNC)
SFN Reset Output
(DATA OUT
Rear-Panel BNC)
Uplink
Long Code Phase
at RF
10 ms
Trigger Delay
+
TSector
FN = 0
FN = 12
16
-1
Reference Uplink
Long Code Phase
10 ms
Trigger Delay
(-50 to 204 chips)
+
TSector
(0 to 2560 chips)
-50 to 2764 chips
24 chips
SFN RST to
RF Delay
0
1280 chips0
TSlot +
TFrame
TSlot, TFrame
Channels 1, 2, 3
Frame Timing
at RF
TSlot Range: 32 ksps 0 to 19 symbols
64 ksps 0 to 39 symbols
128 ksps 0 to 79 symbols
256 ksps 0 to 159 symbols
TFrame Range: 0 to 15 slots
TSector Range: 0 to 2560 chips
Trigger Delay Range: -50 to 204 chips
24 chips
SFN RST to RF Delay
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