Using Wideband CDMA ESG-D Series Option H98 Signal Generators
Rear-Panel Overview
3-12 Manual Supplement
5. DATA CLK OUT Connector (8 kHz Out)
This signal is high during half (62.5µs) of the 125µs cycle.
NOTE The signal edges are referenced to the output of the data generator,not
to the outputs of the baseband generator or the RF section. The delay
from the data generator output to the RF section output is
approximately 24 chips.
7. DATA OUT Connector (System Frame Number Reset Out)
This signal goes high for 10 ms during frame number “2
16
− 1” (65,535). The signal goes
low the following frame (frame number 0), and remains low until frame number “2
16
− 1”
occurs again.
NOTES In uplink mode, signal edges are referenced to the output of the data
generator,not to the outputs of the baseband generator or the RF
section. The delay from the data generator output to the RF section
output is approximately 24 chips (seeFigure 3-2 on page3-10).
In downlink mode, signal edges are referenced to the output of the RF
section (seeFigure 3-1 on page3-9).
The System Frame Number Reset out timing, referenced to long code
phase, varies with the TSector adjustment.