The CoreSight 10 connector connects to general‑purpose pins on the FPGA. The availability of P-JTAG
or SWD depends on the design which you implement in the FPGA. The MPS2 and MPS2+ FPGA
Prototyping Boards label this connector as PJTAG.
The following figure shows the CoreSight 10 connector.
1 9
2 10
Figure 5-3 CoreSight 10 connector
The following table shows the pin mapping for each SWD and P-JTAG signal on the CoreSight 10
connector J11.
Table 5-3 CoreSight 10 connector, J11, signal list
Pin Signal Pin Signal
1 3V0_OUT 2 SWDIO/TMS
3 GND 4 SWDCLK/TCK
5 GND 6 SWO/TDO
7 KEY 8 NC/TDI
9 GNDDETECT 10 nSRST
Note
• Pins 2, 6, 8 and 10 have pullup resistors to 3V.
• Pins 4 on both connectors have pulldown resistors to GND.
Related information
2.15.3 P-JTAG on page 2-45
2.15.6 Serial Wire Debug on page 2-45
1.3 Location of components on the MPS2 FPGA Prototyping Board on page 1-17
1.4 Location of components on the MPS2+ FPGA Prototyping Board on page 1-19
5.1.4 CoreSight 20 connector
The MPS2 and MPS2+ FPGA Prototyping Boards provide one 3V 20-pin Cortex debug and ETM
connector. The connector supports P-JTAG processor debug to enable connection of DSTREAM or a
compatible third-party debugger. The connector also supports SWD and 4-bit Trace.
The CoreSight 20 connector connects to general‑purpose pins on the FPGA. The availability of P-JTAG,
SWD, or 4-bit Trace depends on the design which you implement in the FPGA. The MPS2 and MPS2+
FPGA Prototyping Boards label this connector as PJTAG.
The following figure shows the CoreSight 20 connector.
1
19
2 20
Figure 5-4 CoreSight 20 connector
5 Signal Descriptions
5.1 Debug connectors
100112_0200_09_en Copyright © 2013–2016, 2018–2020 Arm Limited or its affiliates. All
rights reserved.
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