The following table shows the pin mapping for each SWD, P-JTAG, and 4-bit Trace signal on the
CoreSight 20 connector J1.
Table 5-4 CoreSight 20 connector, J1, signal list
Pin Signal Pin Signal
1 3V0_OUT 2 SWDIO/TMS
3 GND 4 SWDCLK/TCK
5 GND 6 SWO/TDO/EXTa
7 Key1 8 NC/TDI/EXTb
9 GNDDETECT 10 nSRST
11 3V0_OUT 12 TRACECLK
13 3V0_OUT 14 TRACEDATA[0]
15 GND 16 TRACEDATA[1]
17 GND 18 TRACEDATA[2]
19 GND 20 TRACEDATA[3]
Note
• Pins 2, 6, 8, 9 and 10 have pullup resistors to 3V.
• Pin 4 has a pulldown resistor to GND.
Related information
2.15.3 P-JTAG on page 2-45
2.15.4 4-bit Trace on page 2-45
2.15.6 Serial Wire Debug on page 2-45
1.3 Location of components on the MPS2 FPGA Prototyping Board on page 1-17
1.4 Location of components on the MPS2+ FPGA Prototyping Board on page 1-19
5.1.5 MICTOR 38 connector
The MPS2 and MPS2+ FPGA Prototyping Boards provides one 3V 38-pin MICTOR connector that
supports P-JTAG processor debug to enable connection of DSTREAM or a compatible third-party
debugger. The connector also supports 16-bit Trace and SWD.
The MICTOR 38 connector connects to general‑purpose pins on the FPGA. The availability of P‑JTAG,
SWD, and 16-bit Trace depends on the design which you implement in the FPGA. The MPS2 and
MPS2+ FPGA Prototyping Boards label this connector as PJTAG/TRACE.
The following figure shows the MICTOR 38 connector.
2
38
1 37
Figure 5-5 MICTOR 38 connector
5 Signal Descriptions
5.1 Debug connectors
100112_0200_09_en Copyright © 2013–2016, 2018–2020 Arm Limited or its affiliates. All
rights reserved.
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