Citizen CL-S400DT - Clock Circuit; Reset Circuit

Chapter 2 Operating Principles
2-2. Operation of Control Parts
CL-S400DT 2-24
(2) Reset circuit
This circuit performs the system reset.
At power ON, +3.3V gradually increases from 0V. When the voltage at pin 5 (+3.3V) of U3
(Voltage detector) reaches approx. at 2.8V, nRESET33 signal goes from “Low” to “High” after a
delay time (determined by C4 at pin U3) has passed.
While nRESET33 signal is “Low”, the CPU (U1A) and FPGA (U11) are reset. Also, by
nGRESET signal output from the CPU (U1A), the FPGA (U11) and other circuits are reset.
(3) Clock circuit
Crystal oscillator X1 oscillates a 16 MHz clock. This clock is send to the CPU (U1A) and the
CPU generates a 128 MHz internal clock and 64 MHz bus clock.
The 64 MHz bus clock is fed to the FPGA (U11) and other circuits.
Oscillator X2 oscillates a 48 MHz clock used for USB I/F control. It starts oscillation when
UCLKON signal (pin 77) is output from the CPU to X2.
VSS
+3.3V
1
2
4
Voltage Detector
RESET
L : Reset
U1A
CPU
Power ON
Reset
+3.3V
+3.3V
H
L
0V
P52
Output from
pin 4 of U3
G13
B3-17
U11
FPGA
nGRESET
nGRESET
nRESET33
(to other circuits)
L14
B3-29
nRESET33
nRESET33
B3-1
C14
U3
NJU7705F3-28A
C3
VOUT
Cd
VDD
5
28
23
C4
R6
[SA Main PCB]
U1A
CPU
U11
FPGA
X1
R1
C2
BUSCLK
PCD1
88
D15
GND
+3.3V
UCLKON
PCT7
X2
VDD
DSC8002DI1 (48MHz)
STBY
OUT
77
P10
159
C1
BUSCLK
4
1
3
2
+3.3V
R2
R16
R3
B3-6
USBCLK
[SA Main PCB]
16MHz
X1
164
X2
165
(64MHz)
(128MHz)
(16MHz)
(48MHz)
System Clock
Clock for USB
System Clock
Bus Clock
Internal Clock