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Eaton Pow-R-Line SPX0361126 - Page 237

Eaton Pow-R-Line SPX0361126
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www.eaton.com IM02601001E C-65
Modbus Register Maps
9C79 - 9C7A 40058 - 40059 VA-hours, Phase B UINT32 0 to 99999999 VAh per energy format
2
9C7B - 9C7C 40060 - 40061 VA-hours, Phase C UINT32 0 to 99999999 VAh per energy format
2
9C7D - 9C7D 40062 - 40062 Watts, Phase A UINT16 0 to 4095 watts
1
9C7E - 9C7E 40063 - 40063 Watts, Phase B UINT16 0 to 4095 watts
1
9C7F - 9C7F 40064 - 40064 Watts, Phase C UINT16 0 to 4095 watts
1
9C80 - 9C80 40065 - 40065 VARs, Phase A UINT16 0 to 4095 VARs
0= -3000, 2047= 0,
4095= +3000
1
9C81 - 9C81 40066 - 40066 VARs, Phase B UINT16 0 to 4095 VARs
watts, VARs, VAs =
1
9C82 - 9C82 40067 - 40067 VARs, Phase C UINT16 0 to 4095 VARs
3000 * (register - 2047)
/ 2047
1
9C83 - 9C83 40068 - 40068 VAs, Phase A UINT16 2047 to 4095 VAs
1
9C84 - 9C84 40069 - 40069 VAs, Phase B UINT16 2047 to 4095 VAs
1
9C85 - 9C85 40070 - 40070 VAs, Phase C UINT16 2047 to 4095 VAs
1
9C86 - 9C86 40071 - 40071 Power Factor, Phase A UINT16 1047 to 3047 none 1047= -1, 2047= 0,
3047= +1
pf = (register -
2047) / 1000
1
9C87 - 9C87 40072 - 40072 Power Factor, Phase B UINT16 1047 to 3047 none 1
9C88 - 9C88 40073 - 40073 Power Factor, Phase C UINT16 1047 to 3047 none 1
9C89 - 9CA2 40074 - 40099 Reserved N/A N/A none
26
9CA3 - 9CA3 40100 - 40100 Reset Energy Accumulators UINT16 password5
Write-only register;
always reads as 0.
1
Block Size: 100
Reserved Section
Reserved Block
C34C - C3CD 49997 - 50126 Reserved Set to 0. 130
Block Size: 130
Reserved Block
C737 - C7B6 51000 - 51127 Reserved Set to 0. 128
Block Size: 128
End of Map
Data Formats
ASCII ASCII characters packed 2 per register in high, low order and without any termination characters. .
SINT16 / UINT16 16-bit signed / unsigned integer.
SINT32 / UINT32 32-bit signed / unsigned integer spanning 2 registers. The lower-addressed register is the high order half.
FLOAT 32-bit IEEE floating point number spanning 2 registers. The lower-addressed register is the high order half (i.e., contains the exponent).
TSTAMP 3 adjacent registers, 2 bytes each. First (lowest-addressed) register high byte is year (0-99), low byte is month (1-12). Middle register high byte is day(1-31), low byte is
hour (0-23 plus DST bit). DST (daylight saving time) bit is bit 6 (0x40). Third register high byte is minutes (0-59), low byte is seconds (0-59). For example, 9:35:07AM on
October 12, 2049 would be 0x310A, 0x0C49, 0x2307, assuming DST is in effect.

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