Handheld Tester Emulator Test Suite
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Figure 74 - Test G Setup Screen
Figure 75 - Test G In Progress
Active Mode Functionality Test G
Verify TP1 Timeout Error
Verify TP1 timeout error.
Test G is implemented using a standard Load Cycle test. The
Load Cycle screen is displayed, and the HHT advances the
E84 handshake up to the point where the UUT sets it’s L_REQ
signal.
At this point, the HHT locks it’s outputs, and displays a status
message indicating that the TP1 timeout should occur when
the displayed count down timer expires.
The operator must press either the Pass or Fail option (newly
displayed for TP timeout tests) to indicate if the UUT properly
displayed the TP1 timeout error.
When the operator passes the test, the HHT will do one last
verification of the UUT. At the point of the timeout error, the
UUT should drop the HO_AVBL signal to indicate the error
condition. The HHT will verify that the HO_AVBL signal is OFF.
If it is still ON when the operator presses the Pass option, the
HHT will fail the test.
The UUT must be reset following each TP timeout test.
Handheld Tester Emulator Test Suite
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PAGE 82
Figure 76 - Test H Setup Screen
Figure 77 - Test H In Progress
Active Mode Functionality Test H
Verify TP2 Timeout Error
Verify TP2 timeout error.
Test H is implemented using a standard Load Cycle test. The
Load Cycle screen is displayed, and the HHT advances the
E84 handshake up to the point where the UUT sets it’s READY
signal.
At this point, the HHT locks it’s outputs, and displays a status
message indicating that the TP2 timeout should occur when
the displayed count down timer expires.
The operator must press either the Pass or Fail option (newly
displayed for TP timeout tests) to indicate if the UUT properly
displayed the TP2 timeout error.
When the operator passes the test, the HHT will verify that the
HO_AVBL signal is OFF. If it is still ON when the operator
presses the Pass option, the HHT will fail the test.
The UUT must be reset following each TP timeout test.
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