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IFR 2026 User Manual

IFR 2026
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REMOTE OPERATION
46882/439 5-33
Hardware event registers
These are device-dependent registers and the bits have meanings as shown in the list at the bottom
of the page. Each source (A, B and C) has its own set of registers, from which its respective
hardware event register summary bits are jointly summarized in the Status Byte.
# Positive transition sets status
d
0
reverse-power protection tripped d
8
filter unlevelled
d
1
fractional-n loop low d
9
output unleveled
d
2
fractional-n loop high d
10
high power amplifier failed
d
3
external standard missing d
11
alc too high
d
4
external standard frequency too low d
12
alc too low
d
5
external standard frequency too high d
13
dsp not responding
d
6
vxo loop low d
14
rf level uncalibrated
d
7
vxo loop high d
15
not used
<hsb
A
>,<hsb
B
>,<hsb
C
> hardware event register summary bits for each source (A, B and C)
<hsb> hardware event register summary bit (summarizes all sources).
To return status of d
3
,d
4
,d
5
when source selected is B or C, source A hardware status enable register
HSE<nrf> must be set.

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IFR 2026 Specifications

General IconGeneral
BrandIFR
Model2026
CategoryInverter
LanguageEnglish