Intel Agilex Series User Manual

Each 32-byte sub-partition descriptor contains the following information:
Table 48. Sub-partition Descriptor Layout
Offset Size Description
0x00
16 Sub-partition name, including a null string terminator
0x10
8 Sub-partition start offset
0x18
4 Sub-partition length
0x1C
4 Sub-partition flags
Two flags are currently defined:
• System set to 1: Reserved for RSU system. For partition offset value, refer to Table 46 on page 175.
• Read only set to 1: The system protects partition against direct writes.
The Intel Quartus Programming File Generator sets these flags as follows at image creation time, then they are not changed
afterward:
Table 49. Flags Specifying Contents and Access
Partition System Read Only
BOOT_INFO
1 1
FACTORY_IMAGE
1 1
SPT0
1 0
SPT1
1 0
CPB0
1 0
CPB1
1 0
P1
0 0
P2
0 0
Note: In order to successfully update SPTs, the HPS software (U-Boot or Linux) must be configured to have a QSPI erase granularity
of 32 KB or less. When configured with a coarser erase granularity (like 64 KB for example), the operation fails. All supported
flash devices offer erase granularities of 4 KB, 32 KB, and 64 KB, and the default for the current HPS software is 4 KB.
5. Remote System Update (RSU)
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Intel Agilex Series Specifications

General

Architecture	FPGA
AI Tensor Blocks	Yes
Category	FPGA
Family	Agilex
Transceiver Speed	Up to 112 Gbps
Manufacturer	Intel
Series	Agilex
Transceiver Data Rate	Up to 112 Gbps
Memory Support	HBM2E
PCIe Support	PCIe 5.0
Memory	HBM2e
Power Efficiency	Improved over previous generations
Operating Temperature	Commercial, Industrial
Process Technology	10nm