Intel Agilex Series User Manual

Signal Names
Configuration Scheme
Avalon-ST AS x4
x8 x16 x32
SDM_IO16 SDM_IO16
Note:
Intel recommends that you assign the CONF_DONE and INIT_DONE pins to SDM I/O pins 0 or 16. These pins have weak
internal pull-downs resistors. If you cannot use these pins, Intel recommends that you include external 4.7-kΩ pull-down
resistors to avoid false signaling.
Related Information
Intel Agilex Power Management User Guide
For more information about PWRMGT_SCL, PWRMGT_SDA, and PWRMGT_ALERT signals.
2.5.3.1. Specifying Optional Configuration Pins
You enable and assign the SDM I/O pins using the Intel Quartus Prime software.
Complete the following steps to assign these additional configuration pins:
1. On the Assignments menu, click Device.
2. In the Device and Pin Options dialog box, select the Configuration category and click Configuration Pins Options.
3. In the Configuration Pin window, enable and assign the configuration pin that you want to include in your design.
2. Intel Agilex Configuration Details
683673 | 2021.10.29
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Configuration User Guide
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Intel Agilex Series Specifications

General

Architecture	FPGA
AI Tensor Blocks	Yes
Category	FPGA
Family	Agilex
Transceiver Speed	Up to 112 Gbps
Manufacturer	Intel
Series	Agilex
Transceiver Data Rate	Up to 112 Gbps
Memory Support	HBM2E
PCIe Support	PCIe 5.0
Memory	HBM2e
Power Efficiency	Improved over previous generations
Operating Temperature	Commercial, Industrial
Process Technology	10nm