Lattice Semiconductor ECP5 - 4 Building Generic High Speed Interfaces; Types of High-Speed DDR Interfaces; Table 4.1. Generic High-Speed I;O DDR Interfaces

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 FPGA-TN-02035-1.3
4. Building Generic High Speed Interfaces
This section describes in detail on how the high-speed interfaces that can be built using the building blocks described in
the section above. The Clarity Designer tool in Lattice Diamond design software builds these interfaces based on
external interface requirements.
4.1. Types of High-Speed DDR Interfaces
This section describes the different types of high-speed DDR interfaces available in ECP5 and ECP5-5G devices.
Table 4.1 lists these interfaces. The naming conventions use for each interface are provided below the table.
Table 4.1. Generic High-Speed I/O DDR Interfaces
Mode
Interface Name
Description
Receive SDR
GIREG_RX.SCLK
SDR Input register using SCLK.
Receive DDRX1 Aligned
GDDRX1_RX.SCLK.Aligned
DDR 1x Input using SCLK. Data is edge-to-edge with incoming clock.
DLLDEL is be used to shift the incoming clock.
Receive DDRX1 Centered
GDDRX1_RX.SCLK.Centered
DDR x1 Input using SCLK. Clock is already centered in data window.
Receive DDRX2 Aligned
GDDRX2_RX.ECLK.Aligned
DDR x2 Input using ECLK. Data is edge-to-edge with incoming clock.
Generic DDR X2 using Edge Clock. DLLDEL is be used to shift the
incoming clock.
Receive DDRX2 Centered
GDDRX2_RX.ECLK.Centered
DDR x2 Input using ECLK. Clock is already centered in data window.
Receive DDRX2 MIPI
GDDRX2_RX.MIPI
DDRx2 Input using ECLK interfaces to MIPI interface. This uses
additional IMIPI module for the interface.
Receive DDRX71
GDDRX71_RX.ECLK
DDR 7:1 input using ECLK.
Transmit SDR
GOREG_TX.SCLK
SDR Output using SCLK. Clock is forwarded through ODDR.
TX DDRX1 Aligned
GDDRX1_TX.SCLK.Aligned
DDR x1 Output using SCLK. Data is edge-on-edge using same clock
through ODDR.
TX DDRX1 Centered
GDDRX1_TX.SCLK.Centered
DDR x1 Output using SCLK. Clock is centered using PLL with different
SCLK.
TX DDRX1 Centered
GDDRX2_TX.ECLK.Aligned
DDR x2 Output that is edge-on-edge using ECLK.
TX DDRX1 Centered
GDDRX2_TX.ECLK.Centered
DDR x2 Output that is pre-centered PLL generated 90o phase, and
output on ECLKs.
TX DDRX71
GDDRX71_TX.ECLK
DDR 7:1 output using ECLK. Data and CLK are aligned on first of 7 bits.
Note: The following describes the naming conventions used for each of the interfaces:
 G – Generic
 IREG – SDR Input I/O Register
 OREG – SDR Output I/O Register
 DDRX1 – DDR 1x gearing I/O Register
 DDRX2 – DDR 2x gearing I/O Registers
 _RX – Receive Interface
 _TX – Transmit Interface
 .ECLK – Uses ECLK (Edge Clock) clocking resource
 .SCLK – Uses SCLK (Primary Clock) clocking resource
 .Centered – Clock is centered to the data when coming into the device