ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 23
Figure 5.12. GDDRX1_TX.SCLK.Centered Interface
Interface Requirement
The clock to the output DDR modules must be routed on the primary clock tree
5.9. GDDRX2_TX.ECLK.Aligned
The interface is used to generate Generic Transmit DDR with 2x gearing using high-speed Edge Clock (ECLK). The
clock output is edge aligned to the data output.
This DDR interface uses the following modules:
ODDRX2Ffor 2x gearing is used to generate the output data.
The high-speed ECLK is routed to the Edge Clock tree through the ECLKSYNCB module.
The SCLK is routed on the primary clock tree and is generated from the ECLK using the CLKDIVF module.
The same ECLK and SCLK are used for both data and clock generation.
The startup synchronization soft IP (GDDRX_SYNC) is required for this interface to tolerate the skew between the
ECLKSYNCB Stop input and the Reset to the DDR and CLKDIV modules.
The ECLKBRIDGE can be optionally enabled if the data bus is crossing over between the left and right sides of the
device. If ECLKBRIDGE is enabled, then the ECLKBRIDGECS element should be used in the interface.
before the ECLKSYNCB element. This element can be enabled through Clarity Designer.
Optionally, you can choose to use the DELAYG or DELAYF element to delay the data output.
The output data can be optionally tristated using either a Tristate input going through an I/O register.
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