ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 45
DDR3, DDR3L, LPDDR2, and LPDDR3 memory interfaces also requires differential DQS signals. The use of
differential DQS is optional for DDR2.
Table 6.4 shows the IO_TYPE setup for each of the DDR memory interfaces.
Table 6.4. I/O Standards for DDR Memory
Note: When implementing the DDR interface, the VREF1 of the bank is used to provide the reference voltage for the interface pins.
6.5. DDR2/DDR3 Memory Interface Termination Guidelines
(These updates are still preliminary. Another update is needed once the whole validation processes are completed.)
Proper termination of a DDR memory interface is an important part of implementation that ensures reliable data
transactions at high-speed. The following sections are the general termination guideline for the ECP5 and ECP5-5G
device DDR memory interface.
6.5.1. Termination for DQ, DQS, and DM
Do not locate any termination on the memory side. The memory side termination on DQ, DQS and DM is
dynamically controlled by the DDR3 SDRAM's ODT function.
Do not locate any termination on the FPGA side. The ECP5 and ECP5-5G device has internal termination on DQ and
DQS, which is dynamically controlled. Use the TERMINATION preference for DQ and DQS pads to enable the
internal parallel termination to VCCIO/2. The TERMINATION preference has the OFF, 50-, 60-, and 75-Ω options.
(Recommended setting for each interface TBD)
6.5.2. Termination for CK
DDR memory clocks require differential termination because they use a differential signaling. Use SSTL15D in DDR3 or
SSTL18D in DDR2 to drive the clock signals. You can locate an effective 100-Ω termination resistance on the memory
side to achieve the differential termination using the following guideline:
Locate a 100-Ω resistor between the positive and negative clock signal, OR
Connect one end of an Rtt resistor to the positive pin and one end of another Rtt to the negative pin of a CK pair,
then connect the other ends of two Rtt resistors together and return to VDD or GND through a Ctt capacitance.
Note that the JEDEC CK termination scheme defined in the DIMM specifications uses 36-Ω for Rtt with 0.1 µF Ctt
for DIMM for DDR3 DIMMs returning to VDD. 50-Ω Rtt can also be used for non-DIMM applications.
Use of series termination resistors at the FPGA side is not recommended.
When fly-by wiring is used in DDR3, the CK termination resistor should be located after the last DDR3 SDRAM device.
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