Lattice Semiconductor ECP5 - Generic DDR Input and Output Primitives; Input DDR Primitives; Iddrx1 F; Figure 8.5. IDDDRX1 F Primitive

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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68 FPGA-TN-02035-1.3
Table 8.8. DLLDELD Attributes
Attribute
Description
Values
Default
DEL_ADJ
2
Sign bit for READ delay adjustment, DDR input
PLUS, MINUS
PLUS
DEL_VAL
2
Value of delay for input DDR.
0–255 (PLUS)
1–256 (MINUS)
Note
2
Notes:
1. Attributes are only available through EPIC and ECL Editor. It is recommended that values of this attribute are not updated
without consulting Lattice Semiconductor Technical Support.
2. Default value is set based on device characterization to achieve the 90° phase shift.
8.7. Generic DDR Input and Output Primitives
The ECP5 and ECP5-5G device IDDR/ODDR modules support 2:1, 4:1 and 7:1 gearing modes on the left and right sides
only. IDDR/ODDR modules on the top (and bottom for non-SERDES parts) only supports 2:1 due to lack of Edge Clocks.
The 2:1 is available on each pin. The 4:1 gearing IDDR/ODDR is available on each pin on the left and right. 7:1 gearing
mode is only available per pin pair on the left and right. This means the DDR register of the N side pin is used to
implement 7:1 mode and is not available to you. It is assumed that Generic DDR applications using 7:1 model uses a
differential input so it would not require the DDR registers of the N side.
8.8. Input DDR Primitives
The following are the primitives used to implement various Generic DDR Input and Output data.
8.8.1. IDDRX1F
This primitive is used to receive Generic DDR with 1x gearing.
IDDRX1F
SCLK
Q0D
Q1
RST
Figure 8.5. IDDDRX1F Primitive
Table 8.9. IDDRX1F Port List
Port
I/O
Description
D
I
DDR data input
SCLK
I
Primary Clock input
RST
I
Reset to DDR registers
Q0
O
Data at the positive edge of the clock
Q1
O
Data at the negative edge of the clock