Lattice Semiconductor ECP5 - Figure 7.6. Ddr_Generic Configuration Tab; Table 7.2. Ddr_Generic Pre-Configuration Parameters

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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54 FPGA-TN-02035-1.3
Figure 7.5 shows the Pre-Configuration tab for DDR generic interfaces. Table 7.2 explains the various parameters in this
tab.
Table 7.2. DDR_Generic Pre-Configuration Parameters
User Interface Option
Range
Interface Type
Transmit, Receive, Receive MIPI
I/O Standard for this Interface
List of Legal Input or Output Standards
Enable Tristate Control
Enabled, Disabled
Bus Width for this Interface
1 — 256
Clock Frequency for this Interface
3.125 — 400 MHz
200 — 400 MHz (or Receive MIPI)
Interface Bandwidth (Calculated)
Clock Frequency for *2* Bus Width
Clock to Data Relationship at the Pins
Edge-to-Edge, Centered
Centered (for Receive MIPI)
Based on the selections made in the Pre-Configuration tab, the Configuration tab is populated with the selections.
Figure 7.6 shows the Configuration tab for the selection made in Pre-Configuration tab.
Figure 7.6. DDR_Generic Configuration Tab
The check box on the top of this tab indicates that the interface is selected based on entries in the Pre-Configuration
tab. You can choose to change these values by disabling this entry. The best suitable interface is picked based on the
selections made in the Pre-Configuration tab.
Table 7.3 explains the various parameters in the Configuration tab.