Lattice Semiconductor ECP5 - Memory Output DDR Primitives for DQ Output; Oddrx2 Dqa; Memory Output DDR Primitives for DQS Output; Oddrx2 Dqsb

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 75
8.13. Memory Output DDR Primitives for DQ Output
The following are the primitives used to implement various memory DDR output configurations to generate the DQ
outputs.
8.13.1. ODDRX2DQA
This primitive is used to generate DQ data output for DDR2 with x2 gearing and for DDR3 memory interface.
D0
D1
SCLK
RST
Q
ODDRX2DQA
D2
D3
ECLK
DQSW270
Figure 8.13. ODDRX2DQA
Table 8.20. ODDRX2DQA Port List
Port
I/O
Description
D0, D1, D2, D3
I
Data input to the ODDR (D0 is output first, D3 last)
ECLK
I
Fast Edge Clock input
DQSW270
I
Clock that is 90° ahead of clock used to generate the DQS output
SCLK
I
SCLK input
RST
I
Reset input
Q
O
DDR data output on both edges of DQSW270
8.14. Memory Output DDR Primitives for DQS Output
Following are the primitives used to implement the DQS outputs to the DDR memory.
8.14.1. ODDRX2DQSB
This primitive is used to generate DQS clock output for DDR2 and DDR3 memory.
D0
D1
SCLK
RST
Q
ODDRX2DQSB
D2
D3
ECLK
DQSW
Figure 8.14. ODDRX2DQSB Primitive