ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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84 FPGA-TN-02035-1.3
Revision History
Revision 1.3, October 2020
Changed speed to 250 MHz for GDDRX1_RX.SCLK.Centered.
Changed speed to 400 MHz for GDDRX2_RX.ECLK.Centered.
Changed speed to 400 MHz for GDDRX2_RX.ECLK.Aligned.
Changed speed to 400 MHz for GDDRX2_RX.MIPI.
Corrected references to the Timing Analysis for High Speed DDR Interfaces section.
Updated the following figures:
Figure 4, GDDRX1_RX.SCLK.Centered Interface (Static Delay)
Figure 5, GDDRX1_RX.SCLK.Centered Interface (Dynamic Data Delay)
Figure 6, GDDRX1_RX.SCLK.Aligned Interface (Static Delay)
Figure 7, GDDRX1_RX.SCLK.Aligned Interface (Dynamic Data/Clock Delay)
Figure 8, GDDRX2_RX.ECLK.Centered Interface (Static Delay)
Figure 9, GDDRX2_RX.ECLK.Centered Interface (Dynamic Data Delay)
Figure 10, GDDRX2_RX.ECLK.Aligned Interface (Static Delay)
Figure 11, GDDRX2_RX.ECLK.Aligned Interface (Dynamic Data/Clock Delay)
Figure 12, GDDRX2_RX.MIPI
Figure 13, GDDRX71_RX.ECLK Interface
Figure 15, GDDRX1_TX.SCLK.Centered Interface
Figure 16, GDDRX2_TX.ECLK.Aligned Interface
Figure 17, GDDRX2_TX.ECLK.Centered Interface
Figure 18, GDDRX71_TX.ECLK.Centered Interface
Figure 31, DDR2, DDR3/DDR3L, LPDDR2, and LPDDR3 Read Side Implementation
Figure 39, SDR Option Selected in the Catalog tab of Clarity Designer
Figure 41, DDR_Generic Option Selected in the Catalog tab of Clarity Designer
Figure 44, Option Selected in the Catalog tab of Clarity Designer
Figure 46, DDR_MEM Option Selected in the Catalog tab of Clarity Designer
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