Lattice Semiconductor ECP5 - ECP5 Device Overview; Applying Power to the Board; Power Distribution Scheme; FPGA Configuration

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 3
Contents
Acronyms in This Document ................................................................................................................................................. 9
1. Introduction ................................................................................................................................................................ 10
2. External Interface Description .................................................................................................................................... 10
3. High-Speed I/O Interface Building Blocks ................................................................................................................... 11
3.1. Edge Clocks ........................................................................................................................................................ 11
3.2. Primary Clocks ................................................................................................................................................... 11
3.3. DQS Lane ........................................................................................................................................................... 11
3.4. PLL ..................................................................................................................................................................... 12
3.5. DDRDLL .............................................................................................................................................................. 12
3.6. DQSBUF ............................................................................................................................................................. 12
3.7. DLLDEL ............................................................................................................................................................... 13
3.8. Input DDR (IDDR) ............................................................................................................................................... 13
3.9. Output DDR (ODDR) .......................................................................................................................................... 13
3.10. Edge Clock Dividers (CLKDIV) ............................................................................................................................ 13
3.11. Input/Output DELAY .......................................................................................................................................... 13
4. Building Generic High Speed Interfaces ..................................................................................................................... 14
4.1. Types of High-Speed DDR Interfaces ................................................................................................................. 14
5. High-Speed DDR Interface Details .............................................................................................................................. 15
5.1. GDDRX1_RX.SCLK.Centered .............................................................................................................................. 15
5.2. GDDRX1_RX.SCLK.Aligned ................................................................................................................................. 16
5.3. GDDRX2_RX.ECLK.Centered .............................................................................................................................. 17
5.4. GDDRX2_RX.ECLK.Aligned ................................................................................................................................. 18
5.5. GDDRX2_RX.MIPI .............................................................................................................................................. 20
5.6. GDDRX71_RX.ECLK ............................................................................................................................................ 21
5.7. GDDRX1_TX.SCLK.Aligned ................................................................................................................................. 22
5.8. GDDRX1_TX.SCLK.Centered .............................................................................................................................. 22
5.9. GDDRX2_TX.ECLK.Aligned ................................................................................................................................. 23
5.10. GDDRX2_TX.ECLK.Centered .............................................................................................................................. 24
5.11. GDDRX71_TX.ECLK ............................................................................................................................................ 25
5.12. Generic DDR Design Guidelines ........................................................................................................................ 25
5.12.1. Using the High Speed Edge Clock Bridge ...................................................................................................... 25
5.12.2. Receive Interface Guidelines ........................................................................................................................ 26
5.12.3. Transmit interface Guidelines ...................................................................................................................... 26
5.12.4. Clocking Guidelines for Generic DDR Interface ............................................................................................ 26
5.13. Timing Analysis for High Speed DDR Interfaces ................................................................................................ 27
5.13.1. Frequency Constraints .................................................................................................................................. 27
5.13.2. DDR Input Setup and Hold Time Constraints ............................................................................................... 27
5.13.3. DDR Clock to Out Constraints for Transmit Interfaces ................................................................................. 28
6. ECP5 and ECP5-5G Memory Interfaces ...................................................................................................................... 31
6.1. DDR Memory Interface Requirements .............................................................................................................. 33
6.2. Features for Memory Interface Implementation .............................................................................................. 34
6.2.1. DQS Grouping ............................................................................................................................................... 34
6.2.2. DLL-Compensated DQS Delay Elements ....................................................................................................... 35
6.2.3. Data Valid Module ........................................................................................................................................ 35
6.2.4. READ Pulse Positioning Optimization ........................................................................................................... 36
6.2.5. Dynamic Margin Control on DQSBUF ........................................................................................................... 38
6.2.6. Read Data Clock Domain Transfer Using Input FIFO .................................................................................... 38
6.2.7. DDR Input and Output Registers (IDDR/ODDR) ............................................................................................ 38
6.3. Memory Interface Implementation .................................................................................................................. 38
6.3.1. Read Implementation ................................................................................................................................... 38
6.3.2. Write Implementation (DQ, DQS, and DM) .................................................................................................. 40
6.3.3. Write Implementation (DDR2, DDR3/DDR3L Address, Command, and Clock) ............................................ 41