ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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46 FPGA-TN-02035-1.3
6.5.3. Termination for Address, Commands, and Controls
Parallel termination to VTT on address, command and control lines is typically required at the DDR2/DDR3 and
DDR3L memory side.
Locate a 50-Ω parallel-to-VTT resistor (or a best known resistance obtained from your SI simulation) to each
address, command, and control line on the memory side.
Series termination resistors can be optionally used on the address, command and control signals to suppress
overshoot/undershoot and to help decrease overall SSO noise level. 22-Ω or 15-Ωseries termination is
recommended when used.
When fly-by wiring is used in DDR3, the address, command, and control termination resistors should be located
after the last DDR3 SDRAM device.
No termination is required on the LPDDR2 and LPDDR3 CA bus and control lines. They use point-to-point connections.
6.5.4. Termination for DDR3/DDR3L DIMM
The DDR3 DIMMs incorporate internal termination following the requirements defined by the JEDEC DIMM
specification. For this reason, the user termination requirement for the DDR3 DIMM is slightly different from that of
DDR3 SDRAM devices:
Do not locate any termination on the memory side. The memory side termination on DQ, DQS, and DM is
dynamically controlled by the DDR3 SDRAM’s ODT function.
Do not locate differential termination on CK at the memory side because the DIMM already has termination on the
module.
Do not locate parallel termination to VTT on address, command, and control signals at the memory side because
the DIMM already has termination on the module.
Follow the termination for DQ, DQS, and DM guideline above for the FPGA side termination.
6.6. DDR Memory Interface Pinout Guidelines
The ECP5 and ECP5-5G device contains dedicated I/O functions for supporting DDR memory interfaces. The following
pinout rules must be followed to properly use the dedicated I/O functions.
The DQS-DQ association rule must be followed.
All associated DQs (8 or 4) to a DQS must be in the same DQS group.
A data mask (DM) must be part of the corresponding DQS group.
Example: DM[0] must be in the DQS-16 group that has DQ[7:0], DQS[0].
A DQS pad must be allocated to a dedicated DQS True (+) pad.
A DQS# pad is auto-placed when a differential SSTL type (SSTL15D in DDR3, SSTL18D in DDR2, SSTL135D in DDR3L,
and HSUL12D in LPDDR2/LPDDR3) is selected.
Do not assign any signal to a DQS# pad if used as differential strobe. The software automatically places DQS# when
a differential I/O type is applied.
DQS/DQS# pads can be used for other DDR functions. For example, DQS# can be used as a DQ pad for a
nondifferential DQS interface such as DDR2 with single ended strobe. However, a DQS signal must use the
DQS/DQS# pads only.
Data group signals (DQ, DQS, DM) can use any of the left and right sides of the ECP5 and ECP5-5G device as long as
they keep the DQS-DQ association rule.
It is recommended that the CK/CK# outputs be located on the same side where the DQ and DQS pads are located
to minimize the skew.
Place the address, command, and control signals either on the same side as where the DQ and DQS pads are
located or they can be placed on the top side for DDR2, DDR3, and DDR3L memory interfaces.
In DDR3 interface the RST# can be located anywhere an output is available as long as the same I/O Standard as the
memory interface is applicable.
The input reference clock to the PLL must be assigned to use dedicated clock routing. The dedicated PLL input pads
are recommended while PCLK inputs can also be used.
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