Lattice Semiconductor ECP5 - Table 7.6. DDR_MEM Configuration Tab Parameters

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
60 FPGA-TN-02035-1.3
Table 7.6 describes the various settings shown in the Configuration tab.
Table 7.6. DDR_MEM Configuration Tab Parameters
User Interface Option
Description
Values
Default
Interface
DDR memory interface type
DDR2, DDR3, DDR3L, LPDDR2, LPDDR3
DDR2
I/O Buffer Configuration
I/O type configuration for DDR
pins
DDR2: SSTL18_I, STL18_II
DDR3: SSTL15_I, SSTL15_II
DDR3L: SSTL135_I, SSTL135_II
LPDDR2: HSUL12
LPDDR3: HSUL12
DDR2: SSTL18_I
DDR3: SSTL15_I
DDR3L: SSTL135_I
LPDDR2: HSUL2
LPDDR3: HSUL12
DDR Memory Frequency
Target DDR memory interface
frequency
DDR2: 125, 200, 267, 333, 400 (MHz)
DDR3: 300, 400
DDR3L: 300, 400
LPDDR2: 125, 200, 267, 333, 400 (MHz)
LPDDR3: 125, 200, 267, 333, 400 (MHz)
DDR2: 267 MHz
DDR3: 400 MHz
DDR3L: 400 MHz
LPDDR2: 400 MHz
LPDDR3: 400 MHz
System Clock Frequency
Calculated system clock frequency.
Not user-selectable, display only.
SCLK Frequency Value
DDR Memory
Frequency/2
Data Width
DDR memory interface data width
DDR2, DDR3, DDR3L: 8, 16, 24, 32, 40,
48, 56, 64, 72
LPDDR2, LPDDR3: 16, 32
16
Number of DQ per DQS
Number of associated DQ per DQS
pin
DDR2, DDR3, DDR3L: 4, 8
LPDDR2, LPDDR3: 8
8
Total number of DQS
Groups
Total number of DQS groups. Not
user-selectable, display only.
Data width/number of DQ per DQS
group
2
DQS Buffer Configuration
for DDR2
DDR2 DQS I/O buffer type
selection
Single-ended, Differential
Single-ended
Clock/Address/Command
Clock/address/command pins
added with this option checked
ENABLED, DISABLED
DISABLED
Data Mask
Data mask pins added with this
option checked
ENABLED, DISABLED
DISABLED
Enable Dynamic Margin
Control on Clock Delay
Dynamic margin control ports
added with this option checked
ENABLED, DISABLED
DISABLED
Generate PLL with this
module
PLL included with this option
checked
ENABLED, DISABLED
DISABLED
PLL Input Clock Frequency
Input reference clock frequency
10 MHz–400 MHz
—
CLKI Input Buffer Type
The I/O Standard for the PLL
Reference Clock.
List of Legal Input Standards,
None (if coming from fabric)
LVCMOS25
Actual DDR Memory
Frequency
Calculated actual memory bus
frequency. Not user-selectable,
display only.
—
—
If you choose to generate the Clock/Address/Command signals, then the settings in the Clock/Address/Command tab
are active and can be set up as required.