ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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56 FPGA-TN-02035-1.3
Displays the achieved PLL output clock
frequency
Actual PLL output Frequency
achieved based on interface
requirement
The I/O Standard for the PLL Reference
Clock
List of Legal Input Standards,
None (if coming from fabric)
Enable MIPI Filter Soft IP
for Low Speed Data
Generates the MIPI Filter soft IP in
module for Interface = Receiver MIPI
Table 7.4 shows how the interfaces are selected by Clarity Designer based on the selections made in the
Pre-Configuration tab.
Table 7.4. Clarity Designer DDR_Generic Interface Selection
Refer to the High-Speed DDR Interface Details section to see implementation details for each of these interfaces.
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