Lattice Semiconductor ECP5 - Figure 5.18. Tco Min and Max Timing Analysis; Figure 5.19. Transmit Centered Interface Timing

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 29
tCOMin = Data cannot transition BEFORE Min
tCOMax = Data cannot transition AFTER Max
tCOMin
CLK
DATA
tCOMax
Figure 5.18. tCO Min and Max Timing Analysis
5.13.3.1. Transmit Centered Interfaces
In this case, the transmit clock is expected to be centered to the data when leaving the device. Figure 5.19 shows the
timing for a centered transmit interface.
tDVBGDDR = Data valid before clock
tDVAGDDR = Data valid after clock
tU = Data transition
t
U
t
DVBCKGDDR
t
DVACKGDDR
t
DVACKGDDR
t
DVBCKGDDR
½ T
Target Edge
CLK
DATA
Figure 5.19. Transmit Centered Interface Timing
Figure 5.19 shows that max value after which the data cannot transition is – tVB_GDDR. The min value before which
the data cannot transition is – (tU+tVB_GDDR). Negative sign is used because in this particular case where clock is
forwarded centered aligned to the data these two conditions occurs before the clock edge.
The ECP5 and ECP5-5G Family Data Sheet (FPGA-DS-02012) specifies the tDVB_GDDRX1/X2 and tDVA_GDDRX1/X2
values at maximum speed. However, we do not have the tU value. Hence, min tCO can be calculated using the
following equation.
tCO Min = - (tVB_GDDRX1/X2 + tU)
½ T = tDVA_GDDRX1/X2 + tVB_GDDRX1/X2 + tU
- (tVB_GDDRX1/X2 + tU) = 1/2T - tDVA_GDDRX1/X2
tCO Min = 1/2T - tDVA_GDDRX1/X2
The clock to out time in the software can be specified as –
CLOCK_TO_OUT PORT “dataout” MAX <-tDVB_GDDRX1/X2> MIN <tDVA_GDDRX1/X2 -1/2 Clock Period> CLKPORT
“clk” CLKOUT PORT “clkout”;
where:
Data = Data Output Port
Clock = Forwarded Clock Output Port
clk = Input Clock Port