ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 19
Dynamic Margin adjustment in the DDRDLLA module can be optionally used to adjust the DDRDLLA delay
dynamically.
The output of the DLLDELD module is also used as the clock input to the DDRDLLA which sends the delay values to the
DLLDELD module. The Receiver Synchronization (RX_SYNC) soft IP is required for the aligned interfaces to prevent
stability issues that may occur due to this loop at startup. The soft IP prevents any updates to the DLLDELD at start until
the DDRDLLA is locked. Once locked the DLLDELD is updated and FREEZE on the DDRDLL is removed. This soft IP is
automatically generated by Clarity Designer.
The following figures show the static delay and dynamic delay options for this interface.
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