Lattice Semiconductor ECP5 - Memory Output DDR Primitives for Tristate Output Control; Tshx2 Dqa; Tshx2 Dqsa; Figure 8.15. TSHX2 DQA Primitive

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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76 FPGA-TN-02035-1.3
Table 8.21. ODDRX2DQA Port List
Port
I/O
Description
D0, D1, D2, D3
I
Data input to the ODDR (D0 is output first, D3 last)
ECLK
I
ECLK input
DQSW270
I
SCLK input
SCLK
I
DQSW includes write leveling phase shift from ECLK
RST
I
Reset input
Q
O
DDR data output on both edges of DQSW
8.15. Memory Output DDR Primitives for Tristate Output Control
The following are the primitives used to implement tristate control for the outputs to the DDR memory.
8.15.1. TSHX2DQA
This primitive is used to generate the tristate control for DQ data output.
T0
T1
SCLK
RST
Q
TSHX2DQA
ECLK
DQSW270
Figure 8.15. TSHX2DQA Primitive
Table 8.22. TSHX2DQA Port List
Port
I/O
Description
T0, T1
I
Tristate input (T0 is output first, followed by T1)
ECLK
I
ECLK input (2x speed of SCLK)
DQSW270
I
Clock that is 90° ahead of the clock used to generate the DQS output
SCLK
I
SCLK input
RST
I
Reset input
Q
O
Tristate output
8.15.2. TSHX2DQSA
This primitive is used to generate the tristate control for DQS output.
T0
T1
SCLK
RST
Q
TSHX2DQSA
ECLK
DQSW
Figure 8.16. TSHX2DQSA Primitive