ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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There is an additional tab called Advanced Settings for the ECP5 and ECP5-5G device that can be used to adjust the
default DQS Read and Write Delay settings.
Figure 7.12. DDR_MEM Advanced Settings Tab
Figure 7.8 shows the available values in this tab.
Table 7.8. DDR_MEM Advanced Settings Tab Parameters
DQS Read Delay Adjustment
Grey out (if DQS Delay Adjustment = FACTORYONLY)
0–255 (if DQS delay adjustment = PLUS)
1–256 (If DQS delay Adjustment = MINUS)
DQS Write Delay Adjustment
Grey out (if DQS Delay Adjustment = FACTORYONLY)
0–255 (if DQS delay adjustment = PLUS)
1–256 (If DQS delay Adjustment = MINUS)
7.6. Building DDR Interfaces in Clarity Designer
After all the DDR Modules are configured, they can be connected up together in the Builder tab of Clarity Designer. The
connections made in the Builder are carried over to the combined HDL file that contains all the DDR module instances.
If the DDR modules were to share resources, the connections for the sharing can be done here.
For example, if a single PLL was shared among the different modules, then the clocks can be connected together in the
Builder tab.
For step by step instructions on using the Builder, refer to the Clarity Designer User Manual.
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