ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 21
5.6. GDDRX71_RX.ECLK
This interface is used to implement 7:1 LVDS Receiver interface using the 1 to 7 gearing with ECLK. Slow speed clock
coming in is multiplied 3.5X using a PLL. This clock is used to capture the data at the receiver IDDRX71 module.
This DDR interface uses the following modules:
IDDRX71B element is used to capture the data.
EHXPLLK multiplies the input clock by 3.5 and phase shift the incoming clock based on the dynamic phase shift
input.
This clock is routed to the Edge Clock (ECLK) clock tree through the ECLKSYNCB module.
CLKDIVF module is used to divide the ECLK by 3.5 and is routed to the primary clock tree used as the SCLK input
A second IDDRX71B element is used with data connected to clock input to generate 7-bit clock phase that can be
used for word alignment.
The startup synchronization soft IP (GDDRX_SYNC) is required for this interface to tolerate the skew between the
ECLKSYNCB Stop input and the Reset to the DDR and CLKDIV modules.
An optional Bit and Word alignment soft IP(BW_ALIGN) can be enabled in Clarity Designer. The Bit alignment
module rotates PLL’s 16 phases to center Edge Clock to middle of data eye and the word alignment module uses
ALIGNWD function of CLKDIVD and IDDRX71B to achieve 7-bit word alignment.
The ECLKBRIDGE can be optionally enabled if the data bus is crossing over between the left and right sides of the
device. If ECLKBRIDGE is enabled, then the ECLKBRIDGECS element should be used in the interface before the
ECLKSYNCB element. This element can be enabled through Clarity Designer.
Figure 5.10. GDDRX71_RX.ECLK Interface
Interface Requirements
The clock input must use a dedicated PLL input pin so it is routed directly to the PLL.
CLKOP output of the PLL must be used as feedback using another Edge Clock tree to compensate for ECLK tree
delay used by CLKOS. Hence this interface uses two ECLK trees.
ECLK must use the Edge Clock tree and the SCLK out of the CLKDIVF must use the Primary Clock tree.
USE PRIMARY preference may be assigned to the SCLK out of the CLKDIVF module.
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