ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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78 FPGA-TN-02035-1.3
9. Soft IP Modules
The following soft IP Modules are available for use with the Generic DDR interfaces described above. All of the soft IP
Modules can be generated using Clarity Designer. Table 9.1 summarizes the list of soft IPs available and the ones that
are optional versus the ones that are automatically generated with the interface in Clarity Designer.
Table 9.1. List of Soft IPs supported
Used to break up the DDRDLL to DLLDEL clock loop for Aligned Interfaces
Needed to tolerate large skew between stop and reset input
Needed to avoid issues on DDR memory bus and update code in operation
without interrupting interface operation.
7:1 LVDS Bit and Word
Alignment (BW_ALIGN)
The soft IP is used to perform bit and word alignment using PLL’s dynamic
phase shift interface and aligned input of IDDR71C.
Implements low pass filter on low speed MIPI data
Table 9.2 summarized the soft IPs used in each interface.
Table 9.2. Soft IP Used in Each Interface
9.1. Detailed Description of Each Soft IP
9.1.1. GDDR_SYNC
This module is needed to startup al RX Centered and all TX interfaces with 2x gearing.
GDDR_SYNC
RST
START
SYNC_CLK
DDR_RESET
STOP
READY
Figure 9.1. GDDR_SYNC Ports
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