ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 71
8.9.3. ODDR71B
This primitive is used for 7:1 LVDS ODDR implementation.
D0, D1, D2, D3, D4, D5, D6
8.10. Memory DDR Primitives
This section describes the primitives used to build DDR2, DDR3, DDR3L, LPDDR2, and LPDDR3 memory interfaces.
8.10.1. DQSBUF (DQS Strobe Control Block)
DQSBUF block is used to delay the incoming DQS signal by 90°. DQSBUF receives a delay code from DDRDLL and shifts
the signal accordingly. There is one DQSBUF block for every 16 I/O. The DQSBUF should be used when the DQS clock
tree is used for clocking the IDDR module.
The following describes the functions of the DQSBUF module:
Receives the delay code from the DDRDLL and generates the 90° delayed DQS signal that is used as a Write clock in
the IDDR module
You can choose to move the delay up or down using the dynamic margin control signals (loadn, move, and
direction).
When this margin control circuit is used and LOADN goes high, any further delay code changes from the DDRDLL
are not reflected in the delay DQS signal. A soft IP is required to detect the code changes from the DDRDLL and
update the MOVE pulse input to the DQSBUF so that the DDRDLL code changes can be tracked.
If margin control is not used, then LOADN should be low to continuously get code from DDRDLL.
Pause should be asserted prior to changing readclksel, DYNDEL<> or DLL code update.
Receives READ clock select signals that are used to correctly position the READ signal with respect to the DQS
preamble
Generates a BURSTDET output that can be used to validate the READ pulse positioning.
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