Lattice Semiconductor ECP5 - Table 9.7. MIPI_FILTER Port Description

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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82 FPGA-TN-02035-1.3
Table 9.7. MIPI_FILTER Port Description
Port
I/O
Description
FILTER_CLK
I
Clock used to drive digital filter. Min freq=100 MHz. Recommendation is to use internal
oscillator at 133 MHz.
LS
I
Low speed signal from MIPI PHY
RST
I
Active high reset. When RST=1, LSOUT=0.
LS_OUT
O
Filtered output signal
cutoff
Parameter
Parameterize the circuit, default=4, pass signal above four cycles.
cutoff=round (20 ns/period (filter_clk)).
Filter_clk=100 MHz, cutoff=4.
Filter_clk=133 MHz, cutoff=6.
Filter_clk=175 MHz, cutoff=7.
Filter_clk=200 MHz. cutoff=8.