Lattice Semiconductor ECP5 - Figure 7.3. SDR Configuration Tab

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02035-1.3 51
Figure 7.3 shows the Configuration tab for SDR module. You can make selections and then click Configure.
Figure 7.3. SDR Configuration Tab