Lattice Semiconductor ECP5 - Memory Output DDR Primitives for Address and Command; Oshx2 A; Figure 8.17. OSHX2 A Primitive; Table 8.23. TSHX2 DQSA Port List

ECP5 and ECP5-5G High-Speed I/O Interface
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Table 8.23. TSHX2DQSA Port List
Port
I/O
Description
T0, T1
I
Tristate input (T0 is output first, followed by T1)
ECLK
I
ECLK input (2x speed of SCLK)
DQSW270
I
Clock that is 90° ahead of the clock used to generate the DQS output
SCLK
I
SCLK input
RST
I
Reset input
Q
O
Tristate output
8.16. Memory Output DDR Primitives for Address and Command
The following are the primitives used to implement the address and command outputs to the DDR memory.
8.16.1. OSHX2A
This primitive is used to generate the address and command for DDR3 memory with x2 gearing and write leveling.
D0
D1
SCLK
RST
Q
OSHX2A
ECLK
Figure 8.17. OSHX2A Primitive
Table 8.24. OSHX2A Port List
Port
I/O
Description
D0, D1
I
Data input (D0 is output first then D1)
ECLK
I
ECLK input (2x speed of SCLK)
SCLK
I
SCLK input
RST
I
Reset input
Q
O
Address and command output