Lattice Semiconductor ECP5 - Table 7.3. Ddr_Generic Configuration Tab Parameters

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 55
Table 7.3. DDR_Generic Configuration Tab Parameters
User Interface Option
Description
Values
Default
Interface selection based
on pre-configuration
Indicates interface is selected based on
selection made in the Pre-configuration
tab. Disabling this checkbox allows you to
make changes if needed.
ENABLED, DISABLED
ENABLED
Interface Type
Type of Interface (Transmit or Receive)
Transmit, Receive, Receive MIPI
Receive
Enable Tristate Control
Generate Tristate control for Transmit
Interfaces
ENABLED, DISABLED
DISABLED
I/O Standard
I/O Standard used for the interface
All Legal Input and Output
standards
LVCMOS25
Clock Frequency
Speed of the Interface
100 MHz–400 MHz (Transmit)
3.125 MHz–400 MHz (Receive)
200 MHz–400 MHz (Receive MIPI)
200 MHz
Gearing Ratio
DDR register gearing ratio
2:1, 4:1
2:1
Alignment
Clock to data alignment
Edge-to-Edge or Centered
Centered
Bus Width
Bus width for each interface
1–256
10
Organize Parallel Data
Allows you to select how the data bits of
the parallel bus should be arranged. You
can choose to set it By Lane where all the
parallel data bits from each lane are
organized together in the data output. If
By Time is chosen instead, a single bit
from each of the data lanes is put
together in the data output.
By Lane, By Time
By Time
Enable ECLK Bridge
(required if bus is
crossing sides)
This is required if the data bus is wide and
is crossing sides.
Enabling this option instantiates the ECLK
Bridge module in the HDL.
Enable, Disable
Disable
Interface
Shows list of all valid high-speed
Interfaces for the given configuration.
Refer to Table 7.4 to see the
interfaces available for a given
configuration.
—
Data Path Delay
Data input can be optionally delayed using
the DELAY block. Default Value is selected
based on Interface Type.
If Interface Type = Receive:
Static Default
Dynamic Default
Static User-Defined
Dynamic User-Defined
If interface type = Receive MIPI
Static Default
Static User-Defined
If Interface Type = Transmit:
Bypass
Static User-Defined
Dynamic User-Defined
If Interface Type
= Receive:
Static Default
If Interface Type
= Transmit:
Bypass
Delay Value for User-
Defined
When Data Path Delay of user-defined is
selected, you also need to set the number
of delay steps to be used.
1–127
1
Enable Dynamic Margin
Control on Clock Delay
Allows dynamic user control on clock
phase shift for Receiver edge to edge
aligned interfaces.
Enable, Disable
Disable
Generate PLL with this
module
When is option is enabled for Transmit
interfaces, the PLL used to generate the
clocks is included in the generated
module.
Enable, Disable
Disable
PLL Input Clock
Frequency
Frequency of the clock used as PLL Input
10 MHz–400 MHz
—