ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
50 FPGA-TN-02035-1.3
7.1. Configuring DDR Modules in Clarity Designer
The catalog section of Clarity Design lists all the DDR architecture modules available on ECP5 and ECP5-5G.
All the DDR modules are located under Architecture Modules – I/O. This includes:
SDR – Select to build SDR Modules.
DDR_GENERIC – Select to build any DDR Generic Receive and Transmit Interfaces.
GDDR_7:1 – Select to build 7:1 LVDS Receiver and Transmit Interface.
DDR_MEM – Select to build DDR Memory Interfaces.
To see the detailed block diagram for each interface generated by Clarity Designer see the High-Speed DDR Interface
Details section.
7.2. Configuring SDR Modules
To build and SDR interface, select SDR option under Architecture Modules – I/O in the Catalog tab of Clarity Designer.
Enter the name of the module. Figure 7.2 shows the type of interface selected as SDR and module name entered. This
module can then be configured by clicking the Customize button.
Figure 7.2. SDR Option Selected in the Catalog Tab of Clarity Designer
To Next Page
Loading...
