Lattice Semiconductor ECP5 - Figure 6.2. Typical LPDDR2;LPDDR3 Memory Interface; Figure 6.3. DQ-DQS During Read; Figure 6.4. DQ-DQS During Write

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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32 FPGA-TN-02035-1.3
FPGA
(DDR Memory Controller)
DQ[7:0]
DQS/DQS#
DM
CA[9:0]
CSN, CKE
ODT(LPDDR3)
CK/CK#
DDR Memory
8/
10/
DQ[7:0]
DQS/DQS#
DM
CA[9:0]
CSN, CKE
ODT(LPDDR3)
CK/CK#
DQ[7:0]
DQS/DQS#
DM
CA[9:0]
CSN, CKE
ODT
CK/CK#
Figure 6.2. Typical LPDDR2/LPDDR3 Memory Interface
DQS(at PIN)
DQ(at PIN)
DQS(at IDDR)
DQ(at IDDR)
90 degree phase shift between DQS pin to IDDR
Preamble
Postamble
Figure 6.3. DQ-DQS During Read
DDR 1 / DDR 2
DDR 3
DQS(at PIN)
DQ(at PIN)
DQS(at PIN)
DQ(at PIN)
Figure 6.4. DQ-DQS During Write
Table 6.1 shows the different DDR memory configurations and features supported by ECP5 and ECP5-5G device.