Lattice Semiconductor ECP5 - Rx_Sync; Figure 9.2. RX_SYNC Ports; Table 9.3. GDDR_SYNC Port List Description; Table 9.4. GDDR_SYNC Port List Description

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 79
Table 9.3. GDDR_SYNC Port List description
Port
I/O
Description
SYNC_CLK
I
Startup clock. This cannot be the RX_CLK or divided version. It can be other low speed
continuously running clock. For example, oscillator clock.
RST
I
Active high reset to this sync circuit. When RST=1, STOP=0, DDR_RESET=1, READY=0.
START
I
Start sync process. This is used to wait for PLL lock, then start sync process in 7:1 LVDS interface.
STOP
O
Connects to ECLKSYNC.STOP
DDR_RESET
O
Reset to all IDDRX or ODDRX components and CLKDIV
READY
O
Indicate that startup is finished and RX circuit is ready to operate.
9.1.2. RX_SYNC
This module is needed to startup RX Aligned interfaces with 2x gearing.
STOP
DLL_LOCK
FREEZE
UDDCNTLN
DLL_RESET
DDR_RESET
SYNC_CLK
RST
UPDATE
READY
RX_SYNC
Figure 9.2. RX_SYNC Ports
Table 9.4. GDDR_SYNC Port List description
Port
I/O
Description
SYNC_CLK
I
Startup clock. This cannot be the RX_CLK or divided version. It can be other low speed
continuously running clock. For example, oscillator clock.
RST
I
Active high reset to this sync circuit. When RST=1, STOP=0, FREEZE=0, UDDCNTLN=1,
DLL_RESET=1, DDR_RESET=1, READY=0.
DLL_LOCK
I
LOCK output from DDRDLL
UPDATE
I
UPDATE can be used to re-start sync process. READY goes low and waits for the sync process to
be completed before going high again. This can only be performed when no traffic is present.
STOP
O
Connect to ECLKSYNC.STOP
FREEZE
O
Connect to DDRDLL.FREEZE
UDDCNTLN
O
Connect to DDRDLL.UDDCNTLN
DLL_RESET
O
Reset to DDRDLL
DDR_RESET
O
Reset to all IDDRX components and CLKDIV
READY
O
Indicate that startup is finished and RX circuit is ready to operate.